The invention relates generally to high-speed switches and more particularly to the use of a high-speed mesh connection to facilitate switching applications.
Most, if not all, high-speed switches in the market today use the cross bar design. The cross bar type switch results in major limitations as to the performance of the system which uses such a switch.
A cross bar switch is an interconnect device which allows only one of the many inputs to send data to each output at a given time. When two or more inputs want to send data to the same output only one is enabled and all the others are blocked. Only one input is available to send data to each output at any given time. This inefficiency degrades the overall performance of the system and requires complex and expensive solutions to cope with the inefficiency.
One typical solution to this problem is to use a fixed cell size. Cells of a fixed size are used instead of packets. This requires each port in the system to implement segmentation and re-assembly (SAR) functions. Generally this is very expensive and difficult to implement at high speeds.
Another solution is to use over speed, meaning using a crowbar switch which supports more than the actual data rate. This is again quite expensive as the user is paying for 2xc3x97 the internal bandwidth but can use only 1xc3x97.
It is an object of the invention to use a cross-switch which allows implementation of very high-speed switches with better functionality and lower-cost than cross bar based solutions.
It is another object of the invention to provide a self routing crossxe2x80x94switch device which allows all the inputs to send data in parallel to the same output and which avoids head of line blocking and avoids the need for expensive solutions.
It is another object of the invention to provide a self routing cross-switch which needs only a small over speed (e.g. in the range of 25 percent) and avoids head of line blocking.
It is a further object of the invention to provide a system which uses a self routing cross-switch device to allow all the inputs to send data in parallel to the same output thereby avoiding head of line blocking and avoiding the need for expensive solutions.
According to the invention, a self routing cross-switch device is provided with a mesh interconnect providing high speed connections (e.g., connections at/or above 10 Gbps). A plurality of input MUX elements are connected to the mesh interconnect. Each MUX element looks at a header of a frame arriving at the input MUX and configures the MUX element to route the frame though the mesh. A plurality of memory output devices are connected to the mesh interconnect. Each output device has a plurality of output first in first out (FIFO) devices for queuing frames arriving at the output memory. Each output first in first out device is associated with one input MUX. A local arbiter is provided for dequeuing frames from each output first in first out device and sending frames to an output.
The cross switch may be provided with pins defining various input/output portions connected to various devices. The devices may have buffer managers associated with the various input/output portions. A back pressure signal may be sent from the output memory device to the ingress buffer manager of the buffer manager unit to indicate that the first in first out (FIFO) device or the output device is above a threshold.
The mesh interconnect provides a direct inter mesh connection from each input MUX to each output block. For example, where seven input/output devices are provided, the mesh interconnect provides seven direct connections from each MUX block to each output block. In this example there are 42 mesh connections for example each running at 10 Gbps. There are a total of 49 FIFOs at the output devices. This is based on a seven by seven (7xc3x977)cross-switch. However, features of the invention are applicable for every reasonable N X N or configuration.
The output from the mesh connections similarly may operate at 10 Gbps. The frames are removed from the FIFOs and sent at the 10 Gbps rate and forwarded to the output FIFO at the 70 Gbps rate. The egress buffer management entity of each input/output buffer manager receives data from the output FIFO at 10 Gbps. The ingress buffer manager sends frames to the input FIFO of the input device at 10 Gbps. Frames are forwarded from the input FIFO to the mux device data rate 10 Gbps.
The arbiter associated with each output block can remove frames from the FIFO based on the priority of the frame. In this way, frames of higher priority are sent to the egress buffer manager of the buffer manager unit before frames of lower priority. Where frames of equal priority are present, a round Robin selection device may be used.
The implementation according to the invention uses a cross-switch which is itself more expensive than a cross bar (the device itself). However, since the performance of the cross-switch according to the invention is much higher than the cross bar the overall cost of the system will be much lower. The cross bar will support 14.28 percent of the bandwidth in the worst-case (for a 7xc3x977 crossbar). The cross-switch of the present invention will support 100 percent of the bandwidth in any scenario.
The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and specific objects attained by its uses, reference is made to the accompanying drawings and descriptive matter in which a preferred embodiment of the invention is illustrated.